Mismatch modeling and characterization of bipolar transistors for statistical CAD

Author

To, Hing-yan ; Ismail, Mohammed

Author_Institution

Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA

Volume

43

Issue

7

fYear

1996

fDate

7/1/1996 12:00:00 AM

Firstpage

608

Lastpage

610

Abstract

A simple test structure and an extraction methodology are presented to study the parameter mismatch variance for vertical npn bipolar transistors. Guidelines for precise and repeatable measurement are discussed, the importance of simultaneous measurement of parameter mismatch is also shown. Mismatch measurements made on 192 BJT pairs fabricated at Orbit, in their 2 μm n-well CMOS process, are used to develop a BJT mismatch variance model and to predict the collector current mismatch deviation of the same population of BJT´s. Comparisons are made with the measured collector current mismatch

Keywords

BiCMOS integrated circuits; bipolar transistors; circuit CAD; semiconductor device models; semiconductor device testing; 2 micron; BJT mismatch variance model; bipolar transistors; collector current mismatch deviation; extraction methodology; mismatch characterization; mismatch modeling; parameter mismatch variance; repeatable measurement; statistical CAD; test structure; vertical n-p-n transistors; Bipolar transistors; Chaos; Circuit simulation; Current measurement; Design engineering; Extraterrestrial measurements; Frequency; Power engineering and energy; Predictive models; Testing;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.508185

Filename

508185