DocumentCode
1082862
Title
A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS
Author
Craninckx, Jan ; Steyaert, Michiel S J
Author_Institution
ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
Volume
31
Issue
7
fYear
1996
fDate
7/1/1996 12:00:00 AM
Firstpage
890
Lastpage
897
Abstract
A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz
Keywords
CMOS digital integrated circuits; flip-flops; frequency synthesizers; prescalers; transceivers; 0.7 micron; 1.75 GHz; 3 V; 8 mA; CMOS; circuit technique; divide-by-two flipflop; dual-modulus divide-by-128/129 prescaler; frequency synthesizers; maximum input frequency; minimum input frequency; transceivers; CMOS process; CMOS technology; Circuits; Frequency conversion; Frequency measurement; Frequency synthesizers; Phase locked loops; Power supplies; Voltage; Voltage-controlled oscillators;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.508200
Filename
508200
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