Title :
A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter
Author :
Roovers, Raf ; Steyaert, Michiel S J
Author_Institution :
ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
fDate :
7/1/1996 12:00:00 AM
Abstract :
A 175 Ms/s A/D converter with a latency of one clock cycle is designed in a 0.7 μm digital CMOS technology. The resolution of the converter is 6 b while the power dissipation is only 160 mW. The A/D converter architecture is based on a continuous time analog preprocessing topology. A continuous time current interpolation circuit is implemented. The performance of the A/D converter is ruled by a tradeoff between speed, power, and accuracy
Keywords :
CMOS integrated circuits; analogue-digital conversion; interpolation; 0.7 micron; 160 mW; 3.3 V; 6 bit; A/D converter; ADC architecture; CMOS ADC; continuous time analog preprocessing topology; continuous time current interpolation circuit; digital CMOS technology; power dissipation; Analog-digital conversion; CMOS technology; Circuits; Clocks; Delay; Digital signal processing; Interpolation; Magnetic heads; Power dissipation; Signal processing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
