Parametric formulation of CMOS latch-up as a function of chip layout parameters

The relationship between the CMOS latch-up characteristics and the chip layout parameters such as the location and spacing of the well and substrate tie-ups (straps) is studied. By measuring the strap current I/sub c/ at varying distances from the well-substrate boundary, it is found that placing these straps at the boundary is most effective. The holding current I/sub h/(x, N) at a point in the circuit is quantitatively related to (1) the distance of x of the well-substrate strap from this point, and (2) the doping level N of the respective region. An analytical expression of the form I/sub h/ (x, N)=e/sup a-b square root x/=I/sub oe//sup -b square root x/ is developed to predict the required frequency of strapping for a particular process technology, where coefficients a and b are functions of the doping. The impact of a strapping scheme on latch-up is explained in terms of a simple engineering model.<>