A serial minded FFT

An FFT algorithm is presented that can be implemented with serial-access memory. For clarity and insight the emphasis is upon conciseness and illustration rather than shorthand mathematical notation. The algorithm´s potential for high-speed implementation is demonstrated by studying variations on the basic algorithm that include both higher radix algorithms and parallel arithmetic unit algorithms. The fact that these sophisticated variations can be seen and understood by inspection of the basic algorithm emphasizes its simplicity. The algorithm is shown very suitable for efficient special-purpose implementation by the functional independence of the transform node from the particular node in the transform or the number of nodes in the transform, i.e., one node in canonical form (for a given radix) represents the entire FFT algorithm. The algorithm is shown to perform variable length transforms at full operational efficiency with minor modification, thus emphasizing its relative versatility. The possibly unexpected conclusion is made that the FFT implementation using parallel arithmetic units is more efficient in terms of speed and probably design effort and hardware, than one using high radix algorithms.