A 4-kB 500-MHz 4-T CMOS SRAM using low-V/sub THN/ bitline drivers and high-V/sub THP/ latches

The design and physical implementation of a prototypical 500-MHz CMOS 4-T SRAM is presented in this work. The latch of the proposed SRAM cell is realized by a pair of cross coupled high-V/sub THP/ pMOS transistors, while the bitline drivers are realized by a pair of low-V/sub THN/ nMOS transistors. The wordline voltage compensation circuit and bitline boosting circuit, then, are neither needed to enhance the data retention of memory cells. Built-in self-refreshing paths make the data retention possible without the appearance of any external refreshing mechanism. The advantages of dual threshold voltage transistors can be used to reduce the access time, and maintain data retention at the same time. Besides, a new design of cascaded noise-immune address transition detector is also included to filter out the unwanted chip select glitches when the SRAM is asynchronously operated.