Watermark-Induced High-Density Via Failures in Submicron CMOS Fabrication (May 2006)

High via resistance was detected in the high-density via structure in our 0.15-mum back-end-of-line (BEOL) yield monitoring test vehicle. A localized insulating layer was found on top of the plug in test vehicle causing high via resistance. The failure was attributed to watermark-induced contaminants on top of the W plug. It was shown that the failure could be avoided by eliminating watermark formation on the wafer in the post-chemical-mechanical polishing scrub process.