GaAs dynamic memory design

Author

Law, Oscar M K ; Salama, T.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

31

Issue

8

fYear

1996

fDate

8/1/1996 12:00:00 AM

Firstpage

1193

Lastpage

1196

Abstract

Subthreshold leakage loss is a serious problem for GaAs dynamic memory. Since the leakage current in a MESFET is several orders of magnitude higher than that in a MOSFET, it is difficult to retain the charge at dynamic nodes resulting in data storage errors, In order to solve this problem, a novel DRAM architecture is proposed. The design is based on a cell consisting of a MESFET switch and a metal-insulator-metal (MIM) planar capacitor as the storage element. The leakage current is reduced by a level-shift technique and a self-biased transistor is used to maintain the dynamic charge during the sense period. A high performance sense amplifier is used to detect small bit line voltage changes and refresh the stored data. A 1 Kb prototype, fabricated in a 1 μm nonself-aligned GaAs MESFET technology, exhibited a total read/write access time of the order of 3 ns

Keywords

DRAM chips; III-V semiconductors; MESFET integrated circuits; MIM devices; field effect memory circuits; gallium arsenide; integrated circuit design; leakage currents; memory architecture; 1 Kbit; 1 micron; 3.0 ns; DRAM architecture; GaAs; MESFET; MIM planar capacitor; bit line voltage changes; data storage errors; dynamic memory design; dynamic nodes; leakage current; level-shift technique; nonself-aligned MESFET technology; read/write access time; self-biased transistor; subthreshold leakage loss; Gallium arsenide; Leakage current; MESFETs; MIM capacitors; MOSFET circuits; Metal-insulator structures; Random access memory; Subthreshold current; Switches; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.508269

Filename

508269