A New Flip-Flop-Based Transient Power Supply Clamp for ESD Protection

As CMOS technology is scaled, the design of a robust electrostatic-discharge (ESD) protection circuit that is transparent to the main circuit is becoming more challenging. For high- frequency applications where minimum parasitic capacitance is required, diodes along with clamps are a popular ESD protection method. The main challenge in the clamp design is to keep the clamp in "on" mode for the whole ESD event while minimizing area and avoiding false triggering. In this paper, a new clamp that uses a flip-flop to turn on the clamp for the complete ESD event is presented. The trigger circuit is able to keep the clamp on for over 2 mus, and this clamp passes a 3-kV HBM ESD stress. Simulation results show that this clamp is immune to false triggering and power supply noise. Furthermore, the stability problem in clamps is addressed, and the new clamp is shown to be immune to oscillation.