Evidence for two distinct positive trapped charge components in NBTI stressed p-MOSFETs employing ultrathin CVD silicon nitride gate dielectric

Besides the generation of interface states and the associated positive trapped charge (N_tc1), experimental results unambiguously show the generation of another positive trapped charge component (N_tc2) during negative-bias temperature instability (NBTI) stressing of p-MOSFETs employing ultrathin silicon nitride gate dielectric. For a given gate stress voltage, N_tc2 is generated at a much faster rate compared to N_tc1. Under the pulsed gate condition studied, N_tc1 could almost be completely annihilated, regardless of the NBTI stress voltage, whereas only partial annihilation of N_tc2 is observed. This more resistant nature of N_tc2 to post-stress relaxation has serious implications on the dynamic NBTI reliability of these p-MOSFETs.