Title :
Double snapback characteristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design
Author :
Ker, Ming-Dou ; Lin, Kun-Hsien
Author_Institution :
Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
The double snapback characteristic in the high-voltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.
Keywords :
CMOS integrated circuits; MOSFET; electrostatic discharge; protection; semiconductor device models; LDMOS; device simulation; double snapback characteristics; double-diffused drain; electrostatic discharge; high-voltage CMOS integrated circuits; high-voltage nMOSFET; latchup-like danger; lateral diffused MOS; nMOSFET holding voltage; on-chip ESD protection design; power supply voltage; power-rail ESD clamp circuit; snapback breakdown condition; transmission line pulsing stress; Breakdown voltage; CMOS process; CMOS technology; Driver circuits; Electrostatic discharge; MOSFET circuits; Power supplies; Power transmission lines; Protection; Stress; DDD; Double-diffused drain; ESD; LDMOS; electrostatic discharge; high-voltage nMOSFET; latchup; lateral diffused MOS;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2004.833372
