A simplified fully implanted bipolar VLSI technology

An implanted n-p-n bipolar transistor structure named Isoplanar Z II (currently, being marketed as FAST-Z technology) with reduced process and masking steps is described. The simplification is achieved by employing self-aligned-transistor (SAT) masking, ion-implantation techniques to provide impurity doping, and using one common annealing cycle for collector, base, and emitter implantations. The device structure reduces design constraints through use of self-aligned field implantation and SAT mask for contact window definition. Submicrometer emitter widths are obtained by step and repeat optical photolithographic tool and two-dimensional effect on current gain due to sidewall injection is also studied. This technology is used to demonstrate 13-15 ns TAA, 4K static RAM and minimum delay of 250 ps per gate, gate array products.