Statistical leakage current reduction in high-leakage environments using locality of block activation in time domain

This paper describes a new leakage current reduction methodology that can give a statistical leakage current reduction even if the chip is in active mode, as well as in sleep mode. The proposed scheme utilizes a time locality of activation probability of a given circuit block like cache memory characteristics. The leakage cut-off switch is operated by a self-timed sleep timer, which puts the block into sleep mode. By waiting for a certain number of cycles before entering sleep mode, power overhead associated with the sleep and wake-up process is optimized, and its conditional probability is also analyzed. The effectiveness of the proposed scheme is verified by an 8-bit RISC microprocessor using Verilog HDL with real firmware, and demonstrated by a 64-bit carry-look-ahead adder with the self-cut-off switch fabricated with dual-threshold voltage SOI technology. The criterion of the effectiveness of the proposed scheme is also discussed.