Standby power reduction using dynamic voltage scaling and canary flip-flop structures

Lowering V_DD during standby mode reduces power by decreasing both voltage and current. Analysis of flip-flop structures shows how low the voltage can scale before destroying the state information. Measurements of a 0.13-μm, dual-V_T test chip show that reducing V_DD to near the point where state is lost gives the best power savings. We show that "canary" flip-flops provide a mechanism for observing the proximity to failure for the flip-flops. The canary flip-flops enable closed-loop standby voltage scaling for achieving savings near the optimum. This approach potentially provides over 2× higher savings than an optimal open-loop approach without loss of state.