Structural and behavioral synthesis for testability techniques

In this paper, a behavioral synthesis for testability system is presented. In this system, a testability modifier is connected to an existing behavioral level synthesis program, which accepts a circuit´s behavioral description in C or VHDL as input. The outline of the system is as follows: (1) a testability analyzer is first applied to identify the hard-to-test areas in the circuit from the behavioral description; (2) a selection process is then applied to select test points or partial scan flip-flops. Selection is based on behavioral information rather than low-level structural description. This allows test point insertion or partial scan usage on circuits described as an interconnection of high level modules; (3) test statement insertion (TSI), an alternative to test point insertion and partial scan, is used to modify the circuit based on the selected test points. The major advantage of using TSI is a low pin count and test application time as compared to test point insertion and partial scan. In addition, TSI can be applied at the early design phase. This approach was implemented in a computer program, and applied to several sample circuits generated by a synthesis tool. The results are also presented