Title :
A sub-mW MPEG-4 motion estimation processor core for mobile video application
Author :
Miyama, Masayuki ; Miyakoshi, Junichi ; Kuroda, Yuki ; Imamura, Kousuke ; Hashimoto, Hideo ; Yoshimoto, Masahiko
Author_Institution :
Fac. of Eng., Kanazawa Univ., Japan
Abstract :
This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a gradient descent search (GDS) algorithm that reduces required computational complexity to 15 MOPS. The GDS algorithm combined with a sub-block search method upgrades picture quality. The quality is almost equal to that of a full search method. An SIMD datapath architecture optimized for the algorithm decreases a clock frequency and supply voltage. A dedicated three-port SRAM macro for image data caches of the processor is newly designed to reduce power consumption. It has been fabricated with 0.18-μm five-layer metal CMOS technology. The VLSI processing QCIF 15-f/s video consumes 0.4-mW power at 0.85-MHz clock frequency with 1.0-V supply voltage. It is applicable to mobile video applications.
Keywords :
CMOS digital integrated circuits; SRAM chips; VLSI; computational complexity; gradient methods; low-power electronics; motion estimation; video coding; 0.18 micron; 0.4 mW; 0.85 MHz; 1.0 V; CMOS technology; MOPS; MPEG-4 motion estimation processor core; MPEG-4 video encoding; SIMD datapath architecture; SRAM macro; VLSI processing QCIF video; clock frequency; computational complexity; gradient descent search algorithm; image data caches; low power consumption; mobile video application; picture quality; subblock search method; supply voltage; CMOS technology; Clocks; Computational complexity; Computer architecture; Encoding; Frequency; MPEG 4 Standard; Motion estimation; Search methods; Voltage; Gradient-based method; MPEG; SIMD; low power; motion estimation;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.831461
