DocumentCode :
1085647
Title :
Package thermal resistance model: dependency on equipment design
Author :
Andrews, James A.
Author_Institution :
Motorola SPS Inc., Phoenix, AZ, USA
Volume :
11
Issue :
4
fYear :
1988
fDate :
12/1/1988 12:00:00 AM
Firstpage :
528
Lastpage :
537
Abstract :
A physical model is used to explain how package thermal resistance can increase by a factor of four even though cooling conditions remain constant. The model accounts for the discrepancy between observed system thermal performance of a package and data sheet thermal resistance values which are not accompanied by qualifying data consisting of chip thermal resistance, board temperature rise over ambient, convection coefficient, mounting sensitivity, and power dissipation. In all, eight constants are needed to predict inherent increases in package thermal resistance when going from a lab condition to an equipment condition. These constants and procedures for obtaining them are given for dual in line (DIP), pin grid array (PGA), small outline transistor (SOT), and plastic leaded chip carrier (PLCC) packages. A foundation is established for routinely including the constants in component data sheets and for strengthening thermal measurement standards
Keywords :
cooling; packaging; thermal resistance; DIP; PGA; PLCC; SOT; board temperature rise; chip thermal resistance; convection coefficient; cooling conditions; data sheet thermal resistance values; dual in line; equipment design; package thermal resistance; pin grid array; plastic leaded chip carrier; small outline transistor; system thermal performance; Cooling; Electronics packaging; Measurement standards; Packaging machines; Plastic packaging; Power dissipation; Power system modeling; Temperature sensors; Thermal factors; Thermal resistance;
fLanguage :
English
Journal_Title :
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
0148-6411
Type :
jour
DOI :
10.1109/33.16694
Filename :
16694
Link To Document :
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