N- and P-well optimization for high-speed N-epitaxy CMOS circuits

A double-well n-epi CMOS process was used to investigate the influence of technological parameters relevant to high-speed performance. Dopant concentrations, well depths, channel lengths, and epi-layer thickness have been varied with regard to low propagation delay times measured by three-input NOR/NAND ring oscillators. Parasitic bipolar effects like latchup have been taken into consideration. Ring oscillator circuits designed in general with 3.5-µm design rules and with geometrical gate lengths ≤2 µm exhibited gate delays ≤0.9 ns. The influence of low temperature processing on short-channel and field oxide transistors is discussed.