Title :
Latchup prevention using an N-well epi-CMOS process
Author :
Holly, Patrick J. ; Akers, Lex A.
Author_Institution :
Motorola, Inc., Mesa, AZ
fDate :
10/1/1983 12:00:00 AM
Abstract :
A n-well epi-CMOS structure is described to reduce the latchup sensitivity of CMOS. Results demonstrate excellent latchup reduction.
Keywords :
Acoustical engineering; Anisotropic magnetoresistance; Conductivity; Electron devices; Latches; Metallization; Plasma applications; Plasma temperature; Substrates; Wet etching;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1983.21308
