On the hardware implementation of digital signal processors

An approach to the machine organization of dedicated hardware digital signal processors is proposed that is based on a specialized representation of the processing coefficients derived from the canonical signed-digit code. This leads to a realization requiting the minimum number of add/subtract operations to mechanize the required multiplications and additions. The proposed organization is shown to be highly modular and well suited to integrated circuit implementation, and offers a significantly better performance when compared with existing realizations using prepackaged multipliers.