DocumentCode :
1087789
Title :
IIIB-8 modeling physical limitations on junction scaling for CMOS
Author :
Fair, R.B. ; Wortman, J.J. ; Liu, Jiangchuan ; Tischler, M. ; Masnari, N.A.
Volume :
30
Issue :
11
fYear :
1983
fDate :
11/1/1983 12:00:00 AM
Firstpage :
1584
Lastpage :
1585
Keywords :
Boron; Furnaces; Implants; Mass spectroscopy; Microelectronics; Rapid thermal annealing; Rapid thermal processing; Scalability; Semiconductor device modeling; Tail;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1983.21370
Filename :
1483271
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1087789
