Low-Power Low-Latency Data Allocation for Hybrid Scratch-Pad Memory

Author

Meikang Qiu ; Zhi Chen ; Meiqin Liu

Author_Institution

Comput. Sci. Dept., Pace Univ., New York, NY, USA

Volume

6

Issue

4

fYear

2014

fDate

Dec. 2014

Firstpage

69

Lastpage

72

Abstract

This letter aims at developing new memory architecture to overcome the daunting memory wall and energy wall issues in multicore embedded systems. We propose a new heterogeneous scratch-pad memory (SPM) architecture that is configured with SRAM, MRAM, and Z-RAM. Based on this architecture, we propose two algorithms: a dynamic programming (MDPDA) and a genetic algorithm (AGADA) to allocate data to different memory banks, therefore, reducing memory access cost in terms of power consumption and latency. Extensive experiments are performed to show the merits of the hybrid SPM memory architecture and the effectiveness of the proposed algorithms.

Keywords

SRAM chips; dynamic programming; embedded systems; genetic algorithms; memory architecture; multiprocessing systems; power aware computing; AGADA; MDPDA; MRAM; SRAM; Z-RAM; adaptive genetic algorithm-for-data allocation; energy wall; heterogeneous scratch-pad memory architecture; hybrid SPM memory architecture; hybrid scratch-pad memory; low-power low-latency data allocation; memory access cost reduction; memory banks; memory wall; multicore embedded systems; multidimensional dynamic programming data allocation; power consumption; Dynamic programming; Genetic algorithms; Memory architecture; Memory management; Multicore processing; Random access memory; Data allocation; dynamic programming; genetic algorithm; hybrid memory; multicore; scratch-pad memory (SPM);

fLanguage

English

Journal_Title

Embedded Systems Letters, IEEE

Publisher

ieee

ISSN

1943-0663

Type

jour

DOI

10.1109/LES.2014.2344913

Filename

6871293