Title :
BiCMOS logic testing
Author :
Levitt, Marc E. ; Roy, Kaushik ; Abraham, Jacob A.
Author_Institution :
Sun Microsyst. Comput. Corp., Mountain View, CA, USA
fDate :
6/1/1994 12:00:00 AM
Abstract :
With the anticipated growth of BiCMOS technology for high-performance ASIC design, the issue of testing takes on great significance. This paper addresses the testing of BiCMOS logic circuits. Since many different implementations of BiCMOS gates have been proposed, four representative ones are studied. The adequacy of stuck-at, quiescent current, and delay testing are examined based on circuit level faults. It is demonstrated that a large portion of the defects cannot be detected by common stuck-at or quiescent current tests since they manifest themselves as delay faults. By using the results presented, the test methodologies and the logic families can be ranked based on fault coverage. This ranking can then be used to help decide which BiCMOS solution is proper for a given application.<>
Keywords :
BiCMOS integrated circuits; application specific integrated circuits; design for testability; fault location; integrated circuit testing; integrated logic circuits; logic testing; BiCMOS logic testing; IC testing; circuit level faults; delay faults; delay testing; fault coverage; quiescent current testing; stuck-at testing; test methodologies; Application specific integrated circuits; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Delay; Fault detection; Logic circuits; Logic testing;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
