A Layered Finite Element Method for Electromagnetic Analysis of Large-Scale High-Frequency Integrated Circuits

A high-capacity electromagnetic solution, layered finite element method, is proposed for high-frequency modeling of large-scale three-dimensional on-chip circuits. In this method, first, the matrix system of the original 3-D problem is reduced to that of 2-D layers. Second, the matrix system of 2-D layers is further reduced to that of a single layer. Third, an algorithm of logarithmic complexity is proposed to further speed up the analysis. In addition, an excitation and extraction technique is developed to limit the field unknowns needed for the final circuit extraction to a single layer only, as well as keep the right-hand side intact during the matrix reduction process. The entire procedure is numerically rigorous without making any theoretical approximation. The computational complexity only involves solving a single layer irrespective of the original problem size. Hence, the proposed method is equipped with a high capacity to solve large-scale IC problems. The proposed method was used to simulate a set of large-scale interconnect structures that were fabricated on a test chip using conventional Si processing techniques. Excellent agreement with the measured data has been observed from dc to 50 GHz