DC holding and dynamic triggering characteristics of bulk CMOS latchup

Improved models for bulk CMOS latchup holding and triggering characteristics are developed and verified experimentally in this work. The roles of collector and base branch resistances are shown to lead to an accurate model for the minimum voltage to sustain latchup, and to an improved understanding of strong versus weak layouts, respectively. New measurement techniques for model parameters are described and used to test the dc model. Latchup triggering by base region (substrate or well) lateral currents is considered in some detail, It is shown that both threshold current levels and minimum turn-on times exist, below which latchup will not occur. Supporting experimental evidence is presented for all of the models.