Adaptive Snoop Granularity and Transactional Snoop Filtering in Hardware Transactional Memory

Hardware transactional memory (HTM) offers a promising parallel programming model for chip multiprocessors. The performance aspect of HTMs has been explored extensively, whereas little research has addressed the power of HTMs. In this paper, we investigate power consumption in HTMs and propose two optimization techniques. The first optimization technique is adaptive snoop granularity (ASG). HTMs rely on cache coherence protocols to detect conflicts and maintain consistency of transactional data. One of the main design issues facing HTMs is the growing number of snoops required to maintain coherency of transactional data. We found that many transactions access consecutive memory locations which are not shared by other transactions. ASG monitors these transactional accesses and dynamically changes snoop granularity to reduce the power of the interconnection network and eliminate needless cache snoops. The second optimization technique is transactional snoop filtering (TSF). TSF dynamically tracks accesses to the coherence caches and eliminates cache snoops that would result in cache misses. TSF relies on small filters to monitor cache addresses. Energy is reduced as accesses to the much more demanding data caches are decreased. We extended the Gem5 simulator to model ASG and TSF. Our simulation results show that ASG and TSF are effective and reduce energy of interconnects and caches up to 44% and 89%, respectively.