Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology

Author

Chen, Jung-Sheng ; Ker, Ming-Dou

Author_Institution

Power Conversion Taiwan, Fairchild Semicond. Corp., Hsinchu, Taiwan

Volume

56

Issue

8

fYear

2009

Firstpage

1774

Lastpage

1779

Abstract

In the nanoscale CMOS technology, the thin gate oxide causes large gate-tunneling leakage. In this brief, the influence of gate-tunneling leakage in the MOS capacitor (used in the loop filter) on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology has been investigated and analyzed. The basic PLL with a second-order loop filter is used to observe the impact of gate-tunneling leakage on the performance degradation of the PLL in a 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate their impact on the PLL performance. The locked time, static phase error, and jitter of the second-order PLL are found to be degraded by the gate-tunneling leakage of the MOS capacitor used in the loop filter.

Keywords

CMOS integrated circuits; MOS capacitors; filters; logic circuits; nanotechnology; phase locked loops; MOS capacitor; gate leakage; gate-tunneling leakage; locked time; nanoscale CMOS technology; oxide thickness; performance degradation; phase-locked loop circuit; second-order loop filter; size 90 nm; static phase error; thin gate oxide; CMOS process; CMOS technology; Circuit optimization; Degradation; Filters; Gate leakage; Jitter; MOS capacitors; Performance analysis; Phase locked loops; Gate-tunneling leakage; MOS capacitor; loop filter; phase-locked loop (PLL);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2009.2022696

Filename

5089438