Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals

Ternary content addressable memory (TCAM) is more susceptible to soft errors than static random access memory (SRAM). The large di/dt issue during comparison operation reduces operating voltage ranges, which in turn reduces soft error immunity. The tight structural coupling of TCAM comparison circuits and memory cells does not allow for an interleaving design scheme in mitigating soft errors. Regular scrubbing of stored content can greatly mitigate the reliability issue caused by soft errors. However, frequent scrubbing can also affect device performance. The scrubbing interval should be determined to facilitate both reliability and performance. This paper proposes a novel, model-based approach that includes both single-bit upsets (SBUs) and multi-cell upsets (MCUs) to determine the scrubbing interval by predictive and probabilistic failure rate analysis. This model uses the compound Poisson (CP) process to count clustered random events, which are common phenomena of soft errors in technologies that use chips under 90 nm. The 20 M TCAM with 90-nm CMOS technology was tested with 180-MeV neutron strikes. The scrubbing interval determined based on the proposed model is applied to the TCAM test results. The failure probabilities based on the CP model showed 31% overestimation on average compared to the same from the test data. Such overestimation is mainly due to the independent upset assumption in the proposed model and can enable use of the model as worst case analysis. The worst case comparison with the test data showed 1.7% overestimation, which can tell the proposed model is effective in predicting upper-bound soft error reliability.