DocumentCode :
1089734
Title :
Simultaneous delay and maximum current calculation in CMOS gates
Author :
Rumin, N.C.
Volume :
28
Issue :
7
fYear :
1992
fDate :
3/26/1992 12:00:00 AM
Firstpage :
682
Lastpage :
684
Abstract :
An accurate and simple technique is presented for computing the delay and the maximum switching current in CMOS gates. The effects of input slope, output load, transistor size, and short circuit current are accounted for. The accuracy is within 10% of the SPICE level-3 model and the speed is more than three orders of magnitude faster than SPICE.
Keywords :
CMOS integrated circuits; delays; electric current; integrated logic circuits; logic gates; CMOS gates; delay; input slope; maximum switching current; output load; short circuit current; simultaneous calculation; transistor size;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19920431
Filename :
133068
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1089734
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