DocumentCode :
1089735
Title :
A lateral metal—insulator—p-Si tunnel transistor
Author :
Shieh, C.-L. ; Wagner, S.
Author_Institution :
Princeton University, Princeton, NJ
Volume :
4
Issue :
7
fYear :
1983
fDate :
7/1/1983 12:00:00 AM
Firstpage :
228
Lastpage :
230
Abstract :
We report the fabrication of a lateral MIS tunnel transistor whose emitter and collector are Al/SiO2/p-Si tunnel junctions. All processing is carried out at room temperature except for the growth of the passivating field oxide. The small signal common emitter current gain is 20. Two coupled gain mechanisms exist for such a lateral MIS tunnel transistor. The first mechanism relies on a high minority-carrier injection ratio of the emitter junction. Second, the minority carriers injected into the reverse-biased collector junction may produce additional gain through multiplication of majority-carrier current. Lateral MIS tunnel transistors on n-Si make use of the second mechanism. Our device takes advantage of the high minority-carrier injection ratio achievable with Al/SiO2/p-Si tunnel junctions.
Keywords :
Annealing; Dielectrics and electrical insulation; Electronic switching systems; Epitaxial growth; Fabrication; Helium; Implants; P-n junctions; Temperature; Tunneling;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/EDL.1983.25714
Filename :
1483458
Link To Document :
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