A 20-Gb/s 1 : 2 Demultiplexer With Capacitive-Splitting Current-Mode-Logic Latches

Author

Chien, Jun-Chau ; Lu, Liang-Hung

Author_Institution

Nat. Taiwan Univ., Taipei

Volume

55

Issue

8

fYear

2007

Firstpage

1624

Lastpage

1632

Abstract

This paper presents a high-speed 1:2 demultiplexer (DEMUX) implemented in a 0.18-mum CMOS process. By employing a capacitive-splitting architecture for the current-mode-logic latches, a significant speed improvement is achieved in the proposed DEMUX. Provided a 2²³ - 1 pseudorandom bit sequence from the pattern generator, the fabricated circuit operates at an input data rate up to 20 Gb/s. The fully integrated DEMUX consumes a dc power of 150 mW from a 2-V supply voltage.

Keywords

CMOS logic circuits; current-mode logic; demultiplexing equipment; flip-flops; optical communication equipment; CMOS process; bit rate 20 Gbit/s; current-mode-logic latches; high-speed 1:2 demultiplexer; pattern generator; power 150 mW; pseudorandom bit sequence; size 180 nm; voltage 2 V; Bandwidth; Broadband amplifiers; CMOS process; CMOS technology; Circuits; Cutoff frequency; Flip-flops; Inductance; Latches; Optical receivers; Bandwidth enhancement; capacitive-splitting latches; current-mode-logic (CML); demultiplexers (DEMUX); high-speed flip-flops; inductive peaking; optical-fiber communications;

fLanguage

English

Journal_Title

Microwave Theory and Techniques, IEEE Transactions on

Publisher

ieee

ISSN

0018-9480

Type

jour

DOI

10.1109/TMTT.2007.902071

Filename

4287160