The optimization of on-resistance in vertical DMOS power devices with linear and hexagonal surface geometries

The on-resistance-area product is calculated for VDMOS high-voltage transistors by three different techniques. The two simpler analytic approaches provide useful approximations to the more accurate simulation. The sheet resistance of the accumulation layer is taken into account and gives rise to an optimum source spacing for minimum on-resistance. Linear and hexagonal surface geometries are compared. The latter is shown to give lower R . A products at certain values of source spacing, but higher values if the source spacing exceeds a critical value.