Layout and bias considerations for preventing transiently triggered latchup in CMOS

This paper investigates several techniques for hardening CMOS curcuitry against transiently triggered latchup. Measurements of critical rise time are made on four variations of the p-n-p-n structure inherent to CMOS. For each structure the n-well and substrate shunt resistances are varied as is the substrate bias. These measurements are performed on both bulk and epi-samples using both topside and backside substrate contacts. Comparison of the parasitic bipolar transistors comprising the p-n-p-n structures reveals that differences in bipolar behavior do not completely explain the differences in p-n-p-n latchup behavior. Test results are used to rate the various hardening techniques.