The AMD Opteron Northbridge Architecture

Author

Conway, Pat ; Hughes, Bill

Author_Institution

Adv. Micro Devices, Sunnyvale

Volume

27

Issue

2

fYear

2007

Firstpage

10

Lastpage

21

Abstract

To increase performance while operating within a fixed power budget, the AMD opteron processor integrates multiple times86-64 cores with a router and memory controller. AMD´s experience with building a wide variety of system topologies using Opteron´s hypertransport-based processor interface has provided useful lessons that expose the challenges to be addressed when designing future system interconnect, memory hierarchy, and I/O to scale with both the number of cores and sockets in future times86-64 CMP architectures.

Keywords

buffer storage; computer architecture; microprocessor chips; multiprocessing systems; resource allocation; AMD Opteron northbridge architecture; AMD opteron processor; hypertransport-based processor interface; memory controller; memory hierarchy; operating performance; system interconnect; system topology; times86-64 CMP architecture; Bandwidth; Blades; Computer architecture; Coprocessors; Delay; Silicon; Sockets; Technological innovation; Throughput; Topology; microarchitecture; northbridge; point-to-point networking; scalability; system topology;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2007.43

Filename

4287392