• DocumentCode
    1091804
  • Title

    Low-Power, High-Performance Architecture of the PWRficient Processor Family

  • Author

    Yeh, Tse-Yu

  • Author_Institution
    Univ. of Michigan, Ann Arbor
  • Volume
    27
  • Issue
    2
  • fYear
    2007
  • Firstpage
    69
  • Lastpage
    78
  • Abstract
    The dual-core PA6T-1682M system on chip (SoC) is the first design in the PWRficient family of high-performance, low-power processor designs that target server-class performance with low power consumption. the heart of the PA6T-1682M is the PA6T core, which implements the 64-bit IBM power architecture. The SoC implements extensive features that support embedded and mobile low-power applications.
  • Keywords
    microprocessor chips; system-on-chip; IBM power architecture; PWRficient processor family; SoC; dual-core PA6T-1682M system on chip; low-power processor; Clocks; Energy consumption; Flip-flops; Heart; Parallel processing; Performance gain; Pipelines; Prefetching; Process design; System-on-a-chip; chip multiprocessor; coherent memory system; computer architecture; high-performance; low power; processor;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2007.37
  • Filename
    4287397