Title :
Design space exploration for real-time embedded stream processors
Author :
Rajagopal, Sridhar ; Cavallaro, Joseph R. ; Rixner, Scott
Abstract :
We explore tradeoffs between organization and number of ALUs and clock frequency in a stream processor. The tool provides candidate low-power configurations and estimates of their real-time performance. The tool relates instruction-level, subword, and data parallelism to functional units´ organization and utilization. The exploration methodology is applicable to all embedded-processor designs in signal and media processing.
Keywords :
Viterbi decoding; digital signal processing chips; embedded systems; instruction sets; parallel architectures; clock frequency; digital signal processing chip; functional units; instruction-level data parallelism; media processing; real-time embedded stream processor design; signal processing; subword parallelism; Arithmetic; Clocks; Design methodology; Digital signal processing; Energy consumption; Frequency; Parallel processing; Signal processing; Space exploration; Streaming media;
Journal_Title :
Micro, IEEE
