The Analysis and Improvement of a Current-Steering DAC´s Dynamic SFDR—II: The Output-Dependent Delay Differences

Author

Chen, Tao ; Gielen, Georges

Author_Institution

ESAT-MICAS, Katholieke Univ., Leuven, Heverlee

Volume

54

Issue

2

fYear

2007

Firstpage

268

Lastpage

279

Abstract

For a current-steering digital-to-analog converter (DAC) without an extra output stage, the variation of the output voltage will result in the variation of the output delay. These output-dependent delay differences will deteriorate the spurious-free dynamic range (SFDR) of a high-speed high-accuracy DAC, especially when glitches exist. In this paper, a convenient mathematical model is presented to analyze during design the impact of this kind of delay differences on the SFDR. The results are verified by comparison to the results of more detailed simulations. Also the impact of glitches on this effect is demonstrated. Possible solutions to reduce this impact are discussed and summarized

Keywords

digital-analogue conversion; high-speed integrated circuits; integrated circuit modelling; SFDR-II; current-steering digital-to-analog converter; high-speed DAC; mathematical model; output-dependent delay difference; spurious-free dynamic range; Communication system control; Delay; Digital-analog conversion; Dynamic range; Impedance; Linearity; Mathematical model; Sampling methods; Switches; Voltage; Current-steering digital-to-analog converters (DACs); glitch; output variation; output-dependent delay difference (ODDD); spurious-free dynamic range (SFDR);

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2006.887598

Filename

4089109