Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time

Author

Nissimoff, Albert ; Martino, Joao Antonio ; Aoulaiche, Marc ; Veloso, A. ; Witters, Liesbeth Johanna ; Simoen, Eddy ; Claeys, Cor

Author_Institution

Electron. Syst. Dept., Univ. of Sao Paulo, São Paulo, Brazil

Volume

35

Issue

6

fYear

2014

fDate

Jun-14

Firstpage

639

Lastpage

641

Abstract

This letter reports on the spike anneal temperature influence on the retention time of 1T-dynamic random access memory cells using a single silicon-on-insulator transistor on ultrathin buried oxide wafers. A 20 °C temperature difference (from 1070 °C to 1050 °C) in the peak process temperature during the spike anneal after the source/drain implantation caused an order of magnitude increment in the retention time. The lower temperature analyzed (1050 °C) increases the retention time up to 100 ms because of the lower drain electrical field and tunneling current.

Keywords

DRAM chips; annealing; silicon-on-insulator; 1T-DRAM retention time; SOI; drain electrical field; drain implantation; dynamic random access memory cells; single silicon-on-insulator transistor; source implantation; spike anneal peak temperature; temperature 1070 degC to 1050 degC; temperature 20 degC; tunneling current; Annealing; Logic gates; Mathematical model; Random access memory; Time measurement; Transistors; Tunneling; 1T-DRAM; 1T-DRAM.; Capacitorless DRAM; SOI;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2014.2319094

Filename

6811203