Title :
Conventional contact interconnect technology as an alternative to contact plug (W) technology for 0.85 μm CMOS EPROM IC devices
Author :
Farahani, M.M. ; Buller, J.F. ; Moore, B.T. ; Garg, S.
Author_Institution :
Adv. Micro Devices Inc., Austin, TX, USA
fDate :
2/1/1994 12:00:00 AM
Abstract :
The conventional (plug-less) and tungsten (W) plug contact interconnect technologies were studied for the fabrication of 0.85 μm CMOS EPROM integrated circuit devices. 4 Mbit EPROM devices and appropriate test structures were fabricated using these two interconnect architectures and were evaluated for process simplicity, associated problems/solutions, contact electrical characteristics, and circuit yield and speed. The most important process issue for the conventional contact technology was the overlay accuracy of the stepper used for printing the contacts. It was found that a misalignment of <0.3 μm was essential if contacts were to be reflowed after the contact etch process in a way that: a) did not violate the geometrical design rules, and b) did not result in bulging of the contacts, or an increase in the contact profile angle which would degrade metal step coverage. Electrical characteristics of the contacts were studied through contact resistance, specific contact resistivity, contact failure rate, and junction leakage measurements for both contact interconnect architectures. The data presented indicated that both processes produced contacts with similar characteristics. Finally, the results of this work indicated that the conventional contact interconnect technology could be reliably used for fabrication of 0.85 μm CMOS EPROM devices. This process was simpler, less expensive, and as structurally reliable as the W contact plug technology
Keywords :
CMOS integrated circuits; EPROM; VLSI; contact resistance; metallisation; 0.85 micron; 4 Mbit; CMOS EPROM IC devices; bulging; circuit yield; contact electrical characteristics; contact failure rate; contact profile angle; contact resistance; conventional contact interconnect technology; geometrical design rules; interconnect architectures; junction leakage measurements; overlay accuracy; process simplicity; CMOS technology; Circuit testing; Contacts; EPROM; Electric variables; Fabrication; Integrated circuit interconnections; Integrated circuit technology; Plugs; Tungsten;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on