Integrated processing of MOS gate dielectric structures

Integrated processing of MOS gate dielectric structures has been carried out in an ultraclean, multichamber processing system as a prototype for cluster (multichamber) processing in order to understand the potential and limitations of cluster processing for this application. With the enhanced surface cleanliness and contamination control enabled in this process environment, etching of the clean Si surface can occur when very low concentrations of oxygen species impinge on the surface at elevated temperatures, an intrinsic consequence of Si-O chemistry. Such etching leads to statistical roughening of the Si surface topography and thereby degrades the electrical properties of subsequently fabricated MOS structures. Identification of the etching reaction leads directly to prescriptions for cluster process integration which prevent etching: (1) ramping up to thermal oxidation temperature in an ambient with sufficient oxygen concentrations; and/or (2) in-situ formation of a passivating oxide surface layer as part of the pre-oxidation cleaning step