A novel SET/MOSFET hybrid static memory cell design

Author

Lee, Bong-Hoon ; Jeong, Yoon-Ha

Author_Institution

Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., Kyungbook, South Korea

Volume

3

Issue

3

fYear

2004

Firstpage

377

Lastpage

382

Abstract

In this paper, a single electron transistor (SET)/metal-oxide-semiconductor field effect transistor (MOSFET)-based static memory cell is proposed. The negative differential conductance (NDC) characteristics of the SET block help us establish the static memory cell circuits more compactly than those in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks exhibiting the NDC. The peak-to-valley current ratio of the SET block is above four with C_G=5.4C_T (C_T=0.1 aF) at T=77K. The read and write operations of the proposed memory cell were validated with SET/MOSFET hybrid simulations at T=77 K. Even though the fabrication process that integrates MOSFET devices and SET blocks with NDC is not yet available, these results suggest that the proposed SET/MOSFET hybrid static memory cell is suitable for a high-density memory system.

Keywords

MOSFET; SPICE; SRAM chips; circuit simulation; electric admittance; network synthesis; single electron transistors; 77 K; MOSFET hybrid static memory cell design; back-back connected single electron transistors; fabrication process; high-density memory system; hybrid simulations; negative differential conductance; peak-valley current ratio; read operation; single electron transistor hybrid static memory cell design; write operation; CMOS logic circuits; CMOS memory circuits; CMOS technology; FETs; Fabrication; MOSFET circuits; Read-write memory; SRAM chips; Single electron transistors; Tunneling; SET; SPICE; SRAM; Single electron transistor; static random access memory;

fLanguage

English

Journal_Title

Nanotechnology, IEEE Transactions on

Publisher

ieee

ISSN

1536-125X

Type

jour

DOI

10.1109/TNANO.2004.828581

Filename

1331327