• DocumentCode
    1092474
  • Title

    FCAT-II: A 50 ns/15 V alterable nonvolatile memory device—Part II: Analysis

  • Author

    Horiuchi, Masatada ; Yamaguchi, Ken ; Kaga, Tohru

  • Author_Institution
    Hitachi Ltd., Tokyo, Japan
  • Volume
    31
  • Issue
    6
  • fYear
    1984
  • fDate
    6/1/1984 12:00:00 AM
  • Firstpage
    739
  • Lastpage
    746
  • Abstract
    An operational model is described for FCAT-II (Floating Si-gate Channel Corner Avalanche Transition-II) nonvolatile memory devices that can perform high-speed write 1 and write 0 operations with 15-V pulses of less than 50-ns duration. The distinct feature of the high-speed write 1 characteristics, including the novel write enable threshold phenomena, are quantitatively analyzed by introducing an equivalent circuit model in which the resistive floating gate over the oxide steps plays an important role as a negative resistance in the transient condition. Transient analyses of the write 1 characteristics are carried out using numerical circuit analysis. Fowler-Nordheim tunnel-governed write 0 characteristics are also evaluated and used for numerical analysis of the write 1 mode. Analytical results have quantitatively good coincidence with experimental results after introduction of a potential raising effect at the floating gate edges, as was predicted in the previous paper [1].
  • Keywords
    Avalanche breakdown; Circuit analysis; Equivalent circuits; Helium; Nonvolatile memory; Numerical analysis; Space vector pulse width modulation; Transient analysis; Tunneling; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1984.21601
  • Filename
    1483886