Realization of digital filters using input-scaled floating-point arithmetic

Fixed-point and floating-point realizations of digital filters are abundant in the literature of digital signal processing. A block-floating-point realization which has some advantages of both fixed-point and floating-point has been reported and compared to fixed-point and floating-point arithmetic with regard to roundoff noise effects. In this paper another alternative realization is proposed which uses input-scaled floating-point arithmetic. A mathematical model is first developed which has some characteristics of both fixed-point and floating-point realizations. Design considerations and theoretical analysis techniques which apply to an input-scaled floating-point realization are presented. A noise model comparison of input-scaled floating-point and block-floating-point realizations is made. Finally, an input-scaled floating-point realization is implemented with a minicomputer and experimental results are shown. It is concluded from the experimental implementation that an input-scaled floating-point structure is a feasible concept which can be implemented with the simplicity of a fixed-point realization, yet it exhibits some desirable characteristics of both fixed-point and floating-point realizations. Also, the implementation of an input-scaled floating-point realization should be simpler than that of block-floating-point because of the simpler scale factor of the former, and an input-scaled floating-point realization characteristically has fewer noise sources than a block-floating-point realization.