DocumentCode
1092962
Title
TaSi2 gate for VLSI CMOS circuits
Author
Schwabe, Ulrich ; Neppl, Franz ; Jacobs, Erwin P.
Author_Institution
Siemens AG, Munich, Federal Republic of Germany
Volume
31
Issue
7
fYear
1984
fDate
7/1/1984 12:00:00 AM
Firstpage
988
Lastpage
992
Abstract
It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n+-poly-Si or polycide gates by TaSi2 . Due to its higher work function, TaSi2 allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n+-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT (L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss , flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2 and n+ -poly Si gate transistors.
Keywords
Degradation; Doping; Electric breakdown; Jacobian matrices; MOSFETs; Stability; Substrate hot electron injection; Subthreshold current; Threshold voltage; Transistors;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1984.21643
Filename
1483928
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