DocumentCode :
1093004
Title :
Top-down pass-transistor logic design
Author :
Yano, Kazuo ; Sasaki, Yasuhiko ; Rikino, Kunihito ; Seki, Koichi
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Volume :
31
Issue :
6
fYear :
1996
fDate :
6/1/1996 12:00:00 AM
Firstpage :
792
Lastpage :
803
Abstract :
The pass-transistor based cell library and synthesis tool are constructed, for the first time, to clarify the potential of top-down pass-transistor logic. The entire scheme is called LEAP (Lean Integration with Pass-Transistors). The feature of a pass-transistor based cell is its multiplexer function and the open-drain structure. This cell has the flexibility of transistor level circuit design and compatibility with conventional cell based design. An extremely simple cell library with only seven cells combined with a synthesis tool called “circuit inventor” is compared with the conventional CMOS library that has over 60 cells combined with the state-of-the-art logic synthesis. The results show that the area, delay, and power dissipation are improved by LEAP and that the value-cost ratio is improved by a factor of three. This demonstrates that LEAP has the potential to achieve a quantum leap in value of LSI´s while reducing the cost. Key issues which have to be cleared before pass transistor logic is used as the generic logic scheme replacing CMOS are also discussed
Keywords :
logic design; LEAP; LSIs; Lean Integration with Pass-Transistors; area; cell library; circuit inventor; delay; logic synthesis; multiplexer function; open-drain structure; power dissipation; synthesis tool; top-down pass-transistor logic design; value-cost ratio; Algorithm design and analysis; CMOS logic circuits; Circuit synthesis; Costs; Hardware design languages; Libraries; Logic circuits; Logic design; Logic functions; MOS devices;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.509865
Filename :
509865
Link To Document :
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