A 2×2 analog memory implemented with a special layout injector

Author

Chai, Yong-Yoong ; Johnson, Louis G.

Author_Institution

Samsung Electron., Seoul, South Korea

Volume

31

Issue

6

fYear

1996

fDate

6/1/1996 12:00:00 AM

Firstpage

856

Lastpage

859

Abstract

Using floating gate MOSFETs, we have designed a 2×2 analog memory, which is expandable to any size array. The reduced programming voltage due to the innovative floating gate MOSFETs enables us to construct the analog memory with a standard double poly n-well process. In addition, a novel programming algorithm is presented. This method will contribute not only to a reduced total programming time, but also to a prolonged lifetime of the memory. The high voltage program/erase pulses are arranged to minimize the disturbance of nonselected cells. The resolution of a memory cell has been found to be 10 mV over a range of 1.25 V to 2 V which is equivalent to the information content of 6 digital cells

Keywords

CMOS analogue integrated circuits; analogue storage; cellular arrays; integrated circuit design; 1.25 to 2 V; analog memory; double poly n-well process; floating gate MOSFETs; layout injector; nonselected cells; programming algorithm; programming voltage; total programming time; Analog memory; Circuits; Fabrication; Nonvolatile memory; Process design; Shape; Signal processing; Signal processing algorithms; Signal resolution; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.509874

Filename

509874