DocumentCode
1093362
Title
Substrate resistance calculation for latchup modeling
Author
Terrill, Kyle W. ; Hu, Chenming
Author_Institution
University of California, Berkeley, CA
Volume
31
Issue
9
fYear
1984
fDate
9/1/1984 12:00:00 AM
Firstpage
1152
Lastpage
1155
Abstract
The input and output circuits are the main triggering mechanisms of latchup in CMOS technology. We have studied the triggering capability of these circuits and the effectiveness of using guard rings to suppress triggering. We present a method to estimate the substrate potential induced by a triggering current in these circuits and the effect of using guard rings to prevent latchup. It was necessary to include effects of the field-threshold implant to obtain good agreement between theory and measurements.
Keywords
CMOS technology; Circuits; Conductivity; Contact resistance; Diodes; Forward contracts; Protection; Surface resistance; Thyristors; Voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1984.21680
Filename
1483965
Link To Document