• DocumentCode
    1093417
  • Title

    Modeling physical limitations on junction scaling for CMOS

  • Author

    Fair, Richard B. ; Wortman, Jimmie J. ; Liu, Jiann ; Tischler, Mike ; Masnari, Nino A.

  • Author_Institution
    Microelectronics Center of North Carolina, Research Triangle Park, NC
  • Volume
    31
  • Issue
    9
  • fYear
    1984
  • fDate
    9/1/1984 12:00:00 AM
  • Firstpage
    1180
  • Lastpage
    1185
  • Abstract
    Accurate calculations of diffusion and ion-implantation processes in silicon require the utilization of complex steady-state physical models that include the effects of both vacancies and self-interstitials. A new one-dimensional computer program, PROSIM II, has been developed for use in experimental junction formation studies that impact on advanced MOS technologies. PROSIM II has been used to study the scaling limits of counter-doped junctions for CMOS using both conventional furnace annealing and rapid thermal annealing processes. It is found that double implants of boron and arsenic can be used to produce a minimum 3000-Å-deep junction and still satisfy sheet resistance requirements for a 1-µm process.
  • Keywords
    Boron; CMOS process; CMOS technology; Furnaces; Implants; Rapid thermal annealing; Rapid thermal processing; Semiconductor device modeling; Silicon; Steady-state;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1984.21685
  • Filename
    1483970