DocumentCode :
1093642
Title :
A new VLSI memory cell using capacitance coupling (CC cell)
Author :
Terada, Kazuo ; Ishijima, Toshiyuki ; Kurosawa, Susumu ; Suzuk, Shun Ichi
Author_Institution :
NEC Corporation, Kawasaki, Japan
Volume :
31
Issue :
9
fYear :
1984
fDate :
9/1/1984 12:00:00 AM
Firstpage :
1319
Lastpage :
1324
Abstract :
A new VLSI memory cell is proposed, which offers a small cell area, about 6F2(F is the feature size), readout signal gain, and high alpha-particle immunity. Since it employs capacitance coupling in a write operation, it requires only one bit line and is called a capacitance coupling (CC) cell. A CC cell consists of three transistors and a capacitor, which are integrated in a small area by sharing their nodes with one another. The charge is stored in a high-concentration p-type diffused layer (p+-layer) in a shallow n-type diffused layer (n-layer). The p+-layer potential controls the readout current which flows through the n-layer. To obtain both the p+-Iayer isolation and the large readout signal, trench isolation was employed. Experimental test devices having 0.7-µm deep n-layer, 0.2-µm deep p+-layer, and 1.5-µm deep trench isolation region were fabricated. They showed complete CC cell operation and "0"/"1" readout current ratio of more than 10.
Keywords :
Coupling circuits; Electrodes; MOSFET circuits; Microelectronics; National electric code; Parasitic capacitance; Testing; Very large scale integration; Voltage control; Writing;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1984.21706
Filename :
1483991
Link To Document :
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