DocumentCode :
1093662
Title :
Low-resistance MOS technology using self-aligned refractory silicidation
Author :
Okabayashi, Hidekazu ; Morimoto, Mitsutaka ; Nagasawa, Eiji
Author_Institution :
NEC Corporation, Kawasaki, Japan
Volume :
31
Issue :
9
fYear :
1984
fDate :
9/1/1984 12:00:00 AM
Firstpage :
1329
Lastpage :
1334
Abstract :
A new low-resistance MOS technology has been developed for use in VLSI´s with scaled MOSFET´s. A new MOSFET is featured by gate and source-drain being refractory silicided in self-alignment and isolated from one another, even without any insulating spacers on gate sides. An essential part of the MOSFET fabrication process is the ion implantation through metal (ITM) silicidation technique, which consists of ion-beam-induced metal-silicon interface mixing and appropriate annealings to form high-quality refractory metal silicides in self-alignment with silicon patterns and with good reproducibility.
Keywords :
Annealing; Fabrication; Insulation; Ion implantation; Isolation technology; MOSFET circuits; Silicidation; Silicides; Space technology; Very large scale integration;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1984.21708
Filename :
1483993
Link To Document :
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